library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity TEST_ALU32 is
end TEST_ALU32;

architecture TESTBENCH of TEST_ALU32 is
component ALU32
    port ( CNTL     : in   unsigned( 1 downto 0);
	   A, B     : in   unsigned(31 downto 0);
	   Y        : out  unsigned(31 downto 0);
	   ZERO     : out  std_logic );
end component;
signal    CNTL          : unsigned(1 downto 0);
signal    ZERO          : std_logic;
signal    A,B,Y         : unsigned(31 downto 0);
begin
	U0: ALU32 port map (CNTL,A,B,Y,ZERO);
	process begin
	    CNTL<= "00";
            A <= "00000000000000000000000000000001";  
	    B <= "00000000000000000000000000000010";
	    wait for 10 ns;
	    CNTL <="01";
	    wait for 10 ns;
	    CNTL <="10";
	    wait for 10 ns;
	    CNTL <="11";
	    wait for 10 ns;
	    CNTL<= "00";
            A <= "00010001000000000000000000000100";  
	    B <= "10010001000000000000000000000100";
	    wait for 10 ns;
	    CNTL <="01";
	    wait for 10 ns;
	    CNTL <="10";
	    wait for 10 ns;
	    CNTL <="11";
	    wait for 10 ns;
	    wait;

	end process;
end TESTBENCH;

configuration CFG_ALU32 of TEST_ALU32 is
    for TESTBENCH
    end for;
end CFG_ALU32;