library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity ALU32 is
    port( CNTL    :  in  unsigned( 1 downto 0);
	  A, B    :  in  unsigned(31 downto 0);
	  Y       :  out unsigned(31 downto 0);
	  ZERO    :  out std_logic );
end entity ALU32;

architecture DATAFLOW  of ALU32 is
signal ytemp : unsigned(31 downto 0);
begin

-- Here, write your description!

end architecture DATAFLOW;