library STD, IEEE;
use STD.TEXTIO.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;

entity TESTBENCH_FF1 is
end TESTBENCH_FF1;

architecture SIM_DATA of TESTBENCH_FF1 is

component AVG4
  port(CLK     : in  std_logic;
       FMINPUT : in  std_logic_vector(7 downto 0);
       AVGOUT  : out std_logic_vector(7 downto 0));
end component;

signal FMINPUT    : std_logic_vector(7 downto 0);
signal AVGOUT     : std_logic_vector(7 downto 0);
signal CLK        : std_logic := '0';

begin

-- Sysetem CLK generation
      CLK <= not CLK after 5 ns;

-- DUT
  U1: AVG4 port map (CLK, FMINPUT, AVGOUT);

-- TEST VECTOR
  P1: process
      file TEST_IN  : text is in "fm.txt";
      variable LINE_IN : line;
      variable V_FMINPUT : std_logic_vector(7 downto 0);
  begin
      readline(TEST_IN, LINE_IN);
      read(LINE_IN, V_FMINPUT);
      FMINPUT <= V_FMINPUT;
      wait for 10 ns;
      if endfile(TEST_IN) then
        wait;
      end if;
  end process;

end SIM_DATA;

configuration CFG_FF1 of TESTBENCH_FF1 is
  for SIM_DATA
  end for;
end CFG_FF1;