library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity AVG4 is
  port(CLK     : in  std_logic;
       FMINPUT : in  std_logic_vector(7 downto 0);
       AVGOUT  : out std_logic_vector(7 downto 0));
end AVG4;

architecture RTL of AVG4 is

signal FF1, FF2, FF3, FF4 : std_logic_vector(7 downto 0);
signal SUM    : std_logic_vector(9 downto 0);

begin

-- SHIFT REGISTER
  process(CLK) begin
    if (CLK'event and CLK = '1') then
       FF1 <= FMINPUT;
       FF2 <= FF1;
       FF3 <= FF2;
       FF4 <= FF3;
    end if;
  end process;

-- SUM
  SUM <= signed(FF1(7)&FF1(7)&FF1)+signed(FF2(7)&FF2(7)&FF2)
        +signed(FF3(7)&FF3(7)&FF3)+signed(FF4(7)&FF4(7)&FF4); 

-- DIVIDE BY 4 (SHIFT 2 bit), OUTPUT REGISTER
  process(CLK) begin
    if (CLK'event and CLK='1') then
        AVGOUT <= SUM(9 downto 2);
    end if;
  end process;

end RTL;