**************************************** Report : timing -path full -delay max -max_paths 1 -sort_by group Design : AVG4 Version: Z-2007.03 Date : Mon Dec 3 05:48:21 2007 **************************************** Operating Conditions: Wire Load Model Mode: top Startpoint: FF1_reg[0] (rising edge-triggered flip-flop clocked by CLK_0) Endpoint: AVGOUT_reg[7] (rising edge-triggered flip-flop clocked by CLK_0) Path Group: CLK_0 Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ AVG4 05x05 class Point Incr Path -------------------------------------------------------------------------- clock CLK_0 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 FF1_reg[0]/CP (FD1) 0.00 0.00 r FF1_reg[0]/Q (FD1) 1.62 1.62 f add_2_root_add_29_3/U36/Z (AN2) 0.97 2.59 f add_2_root_add_29_3/U33/Z (OR2) 0.93 3.52 f add_2_root_add_29_3/U32/Z (AO2) 1.49 5.01 r add_2_root_add_29_3/U29/Z (IV) 0.30 5.31 f add_2_root_add_29_3/U28/Z (OR2) 0.93 6.24 f add_2_root_add_29_3/U27/Z (AO2) 1.49 7.74 r add_2_root_add_29_3/U24/Z (IV) 0.30 8.04 f add_2_root_add_29_3/U23/Z (OR2) 0.93 8.97 f add_2_root_add_29_3/U22/Z (AO2) 1.49 10.46 r add_2_root_add_29_3/U19/Z (IV) 0.30 10.77 f add_2_root_add_29_3/U18/Z (OR2) 0.93 11.70 f add_2_root_add_29_3/U17/Z (AO2) 1.49 13.19 r add_2_root_add_29_3/U14/Z (IV) 0.30 13.49 f add_2_root_add_29_3/U13/Z (OR2) 0.93 14.42 f add_2_root_add_29_3/U12/Z (AO2) 1.49 15.92 r add_2_root_add_29_3/U10/Z (EO) 1.37 17.29 f add_0_root_add_0_root_add_29_3/U14/Z (OR2) 0.93 18.22 f add_0_root_add_0_root_add_29_3/U13/Z (AO2) 1.49 19.71 r add_0_root_add_0_root_add_29_3/U10/Z (IV) 0.30 20.01 f add_0_root_add_0_root_add_29_3/U9/Z (OR2) 0.93 20.95 f add_0_root_add_0_root_add_29_3/U8/Z (AO2) 1.49 22.44 r add_0_root_add_0_root_add_29_3/U5/Z (IV) 0.30 22.74 f add_0_root_add_0_root_add_29_3/U4/Z (OR2) 0.93 23.67 f add_0_root_add_0_root_add_29_3/U3/Z (AO2) 1.18 24.86 r add_0_root_add_0_root_add_29_3/U1/Z (EO) 1.15 26.01 f AVGOUT_reg[7]/D (FD1) 0.00 26.01 f data arrival time 26.01 clock CLK_0 (rise edge) 50.00 50.00 clock network delay (ideal) 0.00 50.00 AVGOUT_reg[7]/CP (FD1) 0.00 50.00 r library setup time -0.80 49.20 data required time 49.20 -------------------------------------------------------------------------- data required time 49.20 data arrival time -26.01 -------------------------------------------------------------------------- slack (MET) 23.19