-- LSI Design Contest in Okinawa 2010
-- testbench_bch.vhd
-- 2009/October/11th
-- TASK: BCH(15,7) 
-- Copyright by  Tom Wada@Univ. of the Ryukyus

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;

entity TESTBENCH_BCH is
end entity TESTBENCH_BCH;

architecture TESTBENCH of TESTBENCH_BCH is
    component ENCODER
	port ( SBWE  : out  std_logic;
	       SB    : out  std_logic;
	       START : out  std_logic;
	       RESET : in   std_logic;
	       CLK   : in   std_logic );
    end component;
--    component DECODER
--	port ( START : in   std_logic;
--	       RBWE  : in   std_logic;
--	       START2: out  std_logic;
--	       RBEC  : out  std_logic;
--	       RESET : in   std_logic;
--	       CLK   : in   std_logic );
--    end component;
    signal     SBWE   :  std_logic;
    signal     SB     :  std_logic;
    signal     START  :  std_logic;
    signal     RESET  :  std_logic := '1';
    signal     CLK    :  std_logic := '0';
    signal     RBEC   :  std_logic;
    signal     START2 :  std_logic;
begin
    -- clock generation
    CLK <= not CLK after 10 ns;

    TX: ENCODER port map 
    (SBWE, SB, START, RESET, CLK);

--    RX: DECODER port map
--    (START, SBWE, START2, RBEC, RESET, CLK);

    process 
    begin
       RESET <= '1';
       wait for 100 ns;
       RESET <= '0';
       wait;
    end process;

end architecture TESTBENCH;

configuration CFG_BCH of TESTBENCH_BCH is
    for TESTBENCH 
    end for;
end configuration CFG_BCH;