-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:52:33 01/24/2012 -- Design Name: -- Module Name: C:/Users/WADA/Xilinx/fft_circuitA/test_fft_circuitA.vhd -- Project Name: fft_circuitA -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: fft_circuitA -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_fft_circuitA IS END test_fft_circuitA; ARCHITECTURE behavior OF test_fft_circuitA IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fft_circuitA PORT( s_re0 : IN std_logic_vector(15 downto 0); s_im0 : IN std_logic_vector(15 downto 0); s_re1 : IN std_logic_vector(15 downto 0); s_im1 : IN std_logic_vector(15 downto 0); s_re2 : IN std_logic_vector(15 downto 0); s_im2 : IN std_logic_vector(15 downto 0); s_re3 : IN std_logic_vector(15 downto 0); s_im3 : IN std_logic_vector(15 downto 0); s_re4 : IN std_logic_vector(15 downto 0); s_im4 : IN std_logic_vector(15 downto 0); s_re5 : IN std_logic_vector(15 downto 0); s_im5 : IN std_logic_vector(15 downto 0); s_re6 : IN std_logic_vector(15 downto 0); s_im6 : IN std_logic_vector(15 downto 0); s_re7 : IN std_logic_vector(15 downto 0); s_im7 : IN std_logic_vector(15 downto 0); G_re0 : OUT std_logic_vector(15 downto 0); G_im0 : OUT std_logic_vector(15 downto 0); G_re1 : OUT std_logic_vector(15 downto 0); G_im1 : OUT std_logic_vector(15 downto 0); G_re2 : OUT std_logic_vector(15 downto 0); G_im2 : OUT std_logic_vector(15 downto 0); G_re3 : OUT std_logic_vector(15 downto 0); G_im3 : OUT std_logic_vector(15 downto 0); G_re4 : OUT std_logic_vector(15 downto 0); G_im4 : OUT std_logic_vector(15 downto 0); G_re5 : OUT std_logic_vector(15 downto 0); G_im5 : OUT std_logic_vector(15 downto 0); G_re6 : OUT std_logic_vector(15 downto 0); G_im6 : OUT std_logic_vector(15 downto 0); G_re7 : OUT std_logic_vector(15 downto 0); G_im7 : OUT std_logic_vector(15 downto 0) ); END COMPONENT; --Inputs signal s_re0 : std_logic_vector(15 downto 0) := (others => '0'); signal s_im0 : std_logic_vector(15 downto 0) := (others => '0'); signal s_re1 : std_logic_vector(15 downto 0) := (others => '0'); signal s_im1 : std_logic_vector(15 downto 0) := (others => '0'); signal s_re2 : std_logic_vector(15 downto 0) := (others => '0'); signal s_im2 : std_logic_vector(15 downto 0) := (others => '0'); signal s_re3 : std_logic_vector(15 downto 0) := (others => '0'); signal s_im3 : std_logic_vector(15 downto 0) := (others => '0'); signal s_re4 : std_logic_vector(15 downto 0) := (others => '0'); signal s_im4 : std_logic_vector(15 downto 0) := (others => '0'); signal s_re5 : std_logic_vector(15 downto 0) := (others => '0'); signal s_im5 : std_logic_vector(15 downto 0) := (others => '0'); signal s_re6 : std_logic_vector(15 downto 0) := (others => '0'); signal s_im6 : std_logic_vector(15 downto 0) := (others => '0'); signal s_re7 : std_logic_vector(15 downto 0) := (others => '0'); signal s_im7 : std_logic_vector(15 downto 0) := (others => '0'); --Outputs signal G_re0 : std_logic_vector(15 downto 0); signal G_im0 : std_logic_vector(15 downto 0); signal G_re1 : std_logic_vector(15 downto 0); signal G_im1 : std_logic_vector(15 downto 0); signal G_re2 : std_logic_vector(15 downto 0); signal G_im2 : std_logic_vector(15 downto 0); signal G_re3 : std_logic_vector(15 downto 0); signal G_im3 : std_logic_vector(15 downto 0); signal G_re4 : std_logic_vector(15 downto 0); signal G_im4 : std_logic_vector(15 downto 0); signal G_re5 : std_logic_vector(15 downto 0); signal G_im5 : std_logic_vector(15 downto 0); signal G_re6 : std_logic_vector(15 downto 0); signal G_im6 : std_logic_vector(15 downto 0); signal G_re7 : std_logic_vector(15 downto 0); signal G_im7 : std_logic_vector(15 downto 0); -- No clocks detected in port list. Replace below with -- appropriate port name constant period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fft_circuitA PORT MAP ( s_re0 => s_re0, s_im0 => s_im0, s_re1 => s_re1, s_im1 => s_im1, s_re2 => s_re2, s_im2 => s_im2, s_re3 => s_re3, s_im3 => s_im3, s_re4 => s_re4, s_im4 => s_im4, s_re5 => s_re5, s_im5 => s_im5, s_re6 => s_re6, s_im6 => s_im6, s_re7 => s_re7, s_im7 => s_im7, G_re0 => G_re0, G_im0 => G_im0, G_re1 => G_re1, G_im1 => G_im1, G_re2 => G_re2, G_im2 => G_im2, G_re3 => G_re3, G_im3 => G_im3, G_re4 => G_re4, G_im4 => G_im4, G_re5 => G_re5, G_im5 => G_im5, G_re6 => G_re6, G_im6 => G_im6, G_re7 => G_re7, G_im7 => G_im7 ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for period*10; -- insert stimulus here --s_re(0) <= 1.0; s_im(0) <= 0.0; --s_re(1) <= 2.0; s_im(1) <= 0.0; --s_re(2) <= 3.0; s_im(2) <= 0.0; --s_re(3) <= 4.0; s_im(3) <= 0.0; --s_re(4) <= 5.0; s_im(4) <= 0.0; --s_re(5) <= 6.0; s_im(5) <= 0.0; --s_re(6) <= 7.0; s_im(6) <= 0.0; --s_re(7) <= 8.0; s_im(7) <= 0.0; s_re0 <= "0000001000000000"; s_im0 <= "0000000000000000"; s_re1 <= "0000010000000000"; s_im1 <= "0000000000000000"; s_re2 <= "0000011000000000"; s_im2 <= "0000000000000000"; s_re3 <= "0000100000000000"; s_im3 <= "0000000000000000"; s_re4 <= "0000101000000000"; s_im4 <= "0000000000000000"; s_re5 <= "0000110000000000"; s_im5 <= "0000000000000000"; s_re6 <= "0000111000000000"; s_im6 <= "0000000000000000"; s_re7 <= "0001000000000000"; s_im7 <= "0000000000000000"; wait; end process; END;