---------------------------------------------------------
--  TESTBENCH program for TRANSMITTER
--  File: test_tx.vhd
--  SYNOPSYS DESIGN CONTEST 2001
--  Tom Wada / Univ. of the Ryukyus 2000/9
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;

entity TEST_TX is
end TEST_TX;

architecture TESTBENCH of TEST_TX is
component TRANSMITTER
    port ( CLK      : in   std_logic;
	   RESET    : in   std_logic;
	   TXOUT    : out  unsigned(1 downto 0);
	   SYNCOUT  : out  std_logic );
end component TRANSMITTER;
signal    CLK           : std_logic := '0';
signal    RESET         : std_logic := '1';
signal    TXOUT         : unsigned(1 downto 0);
signal    SYNCOUT       : std_logic;
signal    cycles        : integer   := 0;
begin
	SEND: TRANSMITTER port map(CLK,RESET,TXOUT,SYNCOUT);

        CLOCK_GEN: process
	begin
	  if (cycles < 1000) then      -- max 1000 cycle 
	       cycles <= cycles +1;
	       wait for 10 ns;
	       CLK <= not CLK;
          else wait;
	  end if;
        end process CLOCK_GEN;

	RESET_GEN: process
	begin
	     LOOP1: for N in 0 to 5 loop
		  wait until falling_edge(CLK);
             end loop LOOP1;
             RESET <= '0';
	end process RESET_GEN;
end TESTBENCH;

configuration CFG_TX of TEST_TX is
    for TESTBENCH
    end for;
end CFG_TX;