# Virtex 4 ML403 Evaluation Platform #Net output<0> LOC=G5 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; #Net output<1> LOC=G6 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; #Net output<2> LOC=A11 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; #Net output<3> LOC=A12 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; Net LED_C LOC=C6 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; Net LED_W LOC=F9 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; Net LED_S LOC=A5 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; Net LED_E LOC=E10 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; Net LED_N LOC=E2 | IOSTANDARD = LVCMOS25 | PULLUP | SLEW = SLOW | DRIVE = 2 | TIG; #Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin; #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; #Net fpga_0_clk_1_sys_clk_pin LOC=AE14 | IOSTANDARD = LVCMOS33; #Net fpga_0_rst_1_sys_rst_pin TIG; #Net fpga_0_rst_1_sys_rst_pin LOC=D6 | PULLUP; Net sysclk TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; Net sysclk LOC=AE14 | IOSTANDARD = LVCMOS33; Net reset TIG; Net reset LOC=D6 | PULLUP;